| Processor name | Intel(R) Celeron(R) CPU 530 @ | |
| 1.73GHz | ||
| Vendor id string | GenuineIntel | |
| CPU Speed | 1856.52Mhz | |
| Maximum level of CPUID | 10 | |
| Maximum level of Extended CPUID | 8 | |
| Family | 6 Extended Family | 0 |
| Model | 6 Extended Model | 1 |
| Stepping | 1 Processor type | 0 |
| Correct family | 6 Correct Model | 22 |
| Features | FPU VME DE PSE TSC MSR PAE MCE CMPXCHG8B |
| APIC SysEnterSysExit MTRR PGE MCA CMOV | |
| PAT PSE36 CLFSH DS ACPI MMX FXSR SSE SSE2 | |
| SS TM PBE | |
| Extended Features | SSE3 DTES64 MONITOR DS-CPL TM2 SSSE3 CMPXCHG16B |
| xTPR PDCM | |
| Misc. features | Intel64 |
| Misc. ext. features | |
| Thermal and Power Management | Digital temperature sensor enabled |
| Maximum virtual byte address size in bits | 48 |
| Maximum physical byte address size in bits | 36 |
| L1 Data TLB number of entries for 4 MB pages | 16 |
| L1 Data TLB associativity for 4 MB pages | 4 |
| Data TLB number of entries for 4 MB pages | 32 |
| Data TLB associativity for 4 MB pages | 4 |
| Ins. TLB number of entries for 4 KB pages | 128 |
| Ins. TLB associativity for 4 KB pages | 4 |
| L1 Data TLB number of entries for 4 KB pages | 16 |
| L1 Data TLB associativity for 4 KB pages | 4 |
| Data TLB number of entries for 4 KB pages | 256 |
| Data TLB associativity for 4 KB pages | 4 |
| L1 instruction cache size in KB | 32 |
| L1 instruction cache associativity | 8 |
| L1 instruction cache line size in bytes | 64 |
| L1 data cache size in KB | 32 |
| L1 data cache associativity | 8 |
| L1 data cache line size in bytes | 64 |
| L2 cache size in KB | 1024 |
| L2 cache associativity | 4 |
| L2 cache line size in bytes | 64 |
| Prefetching in byte | 64 |